1. Field of the Invention:
The invention relates to an integrated circuit and more particularly to an integrated circuit capable of high speed operation and low power dissipation.
2. Description of the Prior Art
In conventional integrated circuits including bipolar transistors, emitter, base and collector of each transistor are usually disposed in one principal surface for simplifying the interconnection of the respective elements. In such arrangements, however, collectors of the respective transistors should be isolated by pn-junctions or oxide (or insulator) regions. This makes the number of manufacturing processes large, and the structure itself complicated and the accurate and rapid manufacture of integrated circuits difficult. FIG. 1 prior art shows part of a conventional integrated circuit. Two transistors Tr.sub.1 and Tr.sub.2 have similar structure. In each transistor, heavily doped n.sup.+ -type regions 2 and 3 are formed in an n-type semiconductor layer 1. The n.sup.+ -type region 2 forms a collector contact region for forming an ohmic metal-semiconductor contact with the collector electrode 4 and another n.sup.+ -type region 3 serves to reduce the collector resistance of the transistor. A p-type base region 5 is formed in a surface portion of the layer 1 on the same side as the collector contact region 2. A heavily doped n.sup.+ -type emitter region 7 is formed in a surface portion of the p-type base region 5. A base electrode 6 and an emitter electrode 8 are formed on the base and the emitter regions 5 and 7. The n-type layer 1 serves as a collector region. Since the transistors Tr.sub.1 and Tr.sub.2 are formed in a same semiconductor wafer adjacent to each other, an isolating p-type region 9 is needed therebeteen for electrically separating the transistors Tr.sub.1 and Tr.sub.2. The isolating p-type region 9 may be replaced by an oxide region or by any high resistivity member.
Suppose that an electronic circuit as shown in FIG. 2 prior art is to be formed in an integrated circuit. When the conventional structure as shown in FIG. 1 is adopted, four discrete transistor structures each being similar to the transistor Tr.sub.1 of FIG. 1 are required for forming four output transistors besides a driving (load) transistor shown on the left side of FIG. 2. Electrical connections among the respective transistors will be achieved with metal layers deposited on the surface. According to such structure, a considerably large area is needed for forming four discrete transistors, each being provided with isolating regions therearound. The total structure of such semiconductor elements and the mutual wiring leads deposited on the surface become also complicated.
For solving the above drawbacks and also for enhancing the operation speed, there have been proposed the integrated injection logic (IIL) circuit or the merged transistor logic (MTL) circuit (C. M. Hart and A. Slob: "Integrated Injection Logic-A New Approach to LSI" ISSCC Tech. Digest, p. 92-93, Feb. 1972, and H. H. Berger and S. K. Wiedman: "Merged Transistor Logic--A Low Cost Bipolar Logic Concept" Ibid, p. 90-91). Usual IIL circuit utilizes the inversely operated multi-collector transistor as shown in FIGS. 3A and 3B, in which FIG. 3A shows the structure in a semiconductor chip and FIG. 3B is the circuit diagram.
Namely, five discrete transistors in FIG. 2 are integrated into one composite structure. In FIG. 3A p-type regions 10 and 11 are formed in an n-type region 1, and n.sup.+ -type regions 13a, 13b, 13c and 13d are formed in the p-type region 11. The p-type region 10, the n-type region 1 and the p-type region 11 constitute emitter, base and collector regions of the injector transistor, while the n-type region 1, the p-type region 11 and the n.sup.+ -type regions 13a to 13d constitute emitter, base and multi-collector regions of the output (switching) multi-collector transistor. No isolating regions one formed in the composite structure. In integrated logic circuits, such composite structures are usually connected sequentially by connecting the collector of the switching transistor to the base of a succeeding switching transistor.
In operation, the injector transistor supplies current to the base region of the switching transistor which is usually connected to the collector of a preceding switching transistor. When the preceding switching transistor is turned off, the collector potential (i.e. V.sub.in) is raised to the high level. The current flowing through the pnp lateral injection transistor, therefore, flows into the base region of the switching transistor. Then, the carriers injected from the pnp injector transistor to the base region of the npn switching transistor raises the base potential and turns the switching transistor on. On the other hand, when the preceding switching transistor is turned on, the collector potential (V.sub.in) is lowered to the low level. Then, the carriers injected from the pnp injector transistor into the base region of the npn switching transistor are allowed to flow through the switching transistor of the preceding stage, without raising the base potential of the switching transistor of the present stage. Thus, an IIL structure performs an inverter action.
In such an integrated injection logic circuit, the structure is greatly simplified as seen in FIG. 3A and also the power-delay product becomes small. However, there still remains the storage effect of minority carriers. Also, in the inversely operated bipolar transistor, the relation of the impurity concentration in the emitter and the collector regions is usually reversed. Therefore, the characteristics of the device become worse, though the elimination of the external emitter wiring often overcomes this drawback.
From the view point of operation speed, bipolar integrated circuits are generally superior to MOS integrated circuits, while the MOS integrated circuits are generally superior to the bipolar integrated circuits with regard to the power dissipation and the packing density.
FIG. 4 shows an example of the characteristic curves of a bipolar transistor, in which the abscissa represents the emitter-collector voltage, and the ordinate the collector current. Connecting a load resistance in series with the collector or with the emitter, the operational characteristic (load line) becomes a line AB or AB', where the point A represents the supply voltage. The operational point moves along the line AB or AB' in accordance with the signal voltage applied between the emitter and the base. In logic circuits, the case where such lines as AB are adopted as the operational line is called unsaturated logic, and the case where such lines as AB' are adopted is called saturated logic. The unsaturated logic has the advantage that the operation speed is high but a disadvantage that the power dissipation is large. While the saturated logic has the advantage that the power dissipation is small, but a disadvantage that the operation speed is low. In either case, the operation speed is almost limited by the storage effect of minority carriers. At the present stage, the time delay (propagation delay) achievable with the IIL circuit is of the order of 10 to 20 nanosec., and the power dissipation per gate is of the order of 100 microwatts (.mu.W), thus the power-delay product ranging around 1 picojule (pJ). In short, in the conventional bipolar transistors, the storage effect of minority carriers is large and limits the operation speed.
For solving this problem, complementary constant current logic (C.sup.3 L) circuits utilizing Schottky junctions in collector junctions have been proposed, but the operation speed thereof is still not high enough.
Furthermore, current mode logic (CML), non-threshold logic (NTL), diode-transistor logic (DTL), direct-coupled transistor logic (DCTL), transistor-transistor logic (TTL), etc. have been developed. But, the power-delay products of these logics are greater at least by one order than that of the IIL circuit at the present stage even if the propagation delay is superior to IIL circuit in the same logic circuits. This is due mainly to the considerable amount of the storage effect of minority carriers and the low integration density.